What is PyHVL?PyHVL is a hardware verification language that combines Python with Verilog. The framework includes the ability to write Verilog PLI applications in Python. PLI applications are foreign C routines that are linked into the Verilog simulator to add new functions to a Verilog program. Such functions can complicated to implement in C but with PyHVL, we provide an object-oriented framework over the basic PLI interface. Through our API, it is possible to write Verilog code that calls Python code. Access to the Verilog scheduler is also possible which provides for callbacks and timeouts in simulated Python tasks. Such simulated tasks can wait (using Python generators) for clock values to change, wait for events to occur, or allow simulation time to pass. The intention of this project is to be an open source replacement for many of the commercial verification languages or at the very least provide many features that are available commercially. The specific goal of this project is to pass TCP, SSL, and TLS traffic through an ASIC using a completely free software stack. From the top level (TLS) down to the Verilog model, every part will be freely available. The example will show that it is possible to test a chip using an open source environment rather than shelling out large sums of money for commercial licenses. It is also a goal to show that a rapid development language such as python can provide the same capabilites as C or C++ but in less time. |